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<a href="#pub-attribs">Data Fields</a>  </div>
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<div class="title">cy_stc_scb_i2c_master_xfer_config_t Struct Reference<div class="ingroups"><a class="el" href="group__group__scb.html">SCB          (Serial Communication Block)</a> &raquo; <a class="el" href="group__group__scb__i2c.html">I2C (SCB)</a> &raquo; <a class="el" href="group__group__scb__i2c__data__structures.html">Data Structures</a></div></div>  </div>
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<a name="details" id="details"></a><h2 class="groupheader">Description</h2>
<div class="textblock"><p>The I2C Master transfer structure. </p>
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Data Fields</h2></td></tr>
<tr class="memitem:ad593c8662c67ee3d7b766d1bfac64639"><td class="memItemLeft" align="right" valign="top"><a id="ad593c8662c67ee3d7b766d1bfac64639"></a>
uint8_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__scb__i2c__master__xfer__config__t.html#ad593c8662c67ee3d7b766d1bfac64639">slaveAddress</a></td></tr>
<tr class="memdesc:ad593c8662c67ee3d7b766d1bfac64639"><td class="mdescLeft">&#160;</td><td class="mdescRight">The 7-bit right justified slave address to communicate with. <br /></td></tr>
<tr class="separator:ad593c8662c67ee3d7b766d1bfac64639"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a17fa9b9a817e002381f07c4982abaffa"><td class="memItemLeft" align="right" valign="top"><a id="a17fa9b9a817e002381f07c4982abaffa"></a>
uint8_t *&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__scb__i2c__master__xfer__config__t.html#a17fa9b9a817e002381f07c4982abaffa">buffer</a></td></tr>
<tr class="memdesc:a17fa9b9a817e002381f07c4982abaffa"><td class="mdescLeft">&#160;</td><td class="mdescRight">The pointer to the buffer for data to read from the slave or data to write into the slave. <br /></td></tr>
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<tr class="memitem:a4afeea04f622380e0c1113cc4bfbdea6"><td class="memItemLeft" align="right" valign="top"><a id="a4afeea04f622380e0c1113cc4bfbdea6"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__scb__i2c__master__xfer__config__t.html#a4afeea04f622380e0c1113cc4bfbdea6">bufferSize</a></td></tr>
<tr class="memdesc:a4afeea04f622380e0c1113cc4bfbdea6"><td class="mdescLeft">&#160;</td><td class="mdescRight">The size of the buffer. <br /></td></tr>
<tr class="separator:a4afeea04f622380e0c1113cc4bfbdea6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a2e158df2a2854d193d589021c2128aa4"><td class="memItemLeft" align="right" valign="top">bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__scb__i2c__master__xfer__config__t.html#a2e158df2a2854d193d589021c2128aa4">xferPending</a></td></tr>
<tr class="memdesc:a2e158df2a2854d193d589021c2128aa4"><td class="mdescLeft">&#160;</td><td class="mdescRight">The transfer operation is pending - the stop condition will not be generated.  <a href="#a2e158df2a2854d193d589021c2128aa4">More...</a><br /></td></tr>
<tr class="separator:a2e158df2a2854d193d589021c2128aa4"><td class="memSeparator" colspan="2">&#160;</td></tr>
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<h2 class="groupheader">Field Documentation</h2>
<a id="a2e158df2a2854d193d589021c2128aa4"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a2e158df2a2854d193d589021c2128aa4">&#9670;&nbsp;</a></span>xferPending</h2>

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          <td class="memname">bool cy_stc_scb_i2c_master_xfer_config_t::xferPending</td>
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<p>The transfer operation is pending - the stop condition will not be generated. </p>
<p>A new transfer starts from start condition and ends with or without stop condition. The stop condition releases I2C bus from master control. When stop is not generated master keeps bus control (transfer is pending) and can issue the next transfer using restart condition instead of start. The I2C driver automatically generates start or restart condition depends on current state. Note if master lost arbitration during transfer it stops control the bus and does not send/receive data or generate stop condition - the transfer ends. </p>

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